1. Field of the Invention
The present invention relates generally to the field of resource sharing for computer systems. More particularly, the present invention relates to the field of resource sharing between or among two or more modules driven at different clock frequencies.
2. Description of Related Art
FIG. 1 illustrates an integrated circuit chip 10 comprising a module 12, a module 14, and a resource 20. Modules 12 and 14 share access to resource 20. Module 12 and resource 20 are driven by a clock signal 32 input to module 12 and to resource 20. Module 14 is driven by a clock signal 34 input to module 14. Clock signals 32 and 34 have different frequencies. Modules 12 and 14 cannot access resource 20 simultaneously.
Because module 14 and resource 20 are driven at different clock frequencies, module 14 accesses resource 20 using clock crossing circuitry 70. Clock crossing circuitry 70 helps manage the cross-over of data and control signals, for example, generated at one clock frequency and received at a different clock frequency. As module 12 and resource 20 are driven at substantially the same clock frequency, module 12 does not require clock crossing circuitry to access resource 20 as module 14 does.
Clock crossing circuitry 70 typically comprises a buffer in which data signals, for example, are input at one clock frequency and output at a different clock frequency. Clock crossing circuitry 70 may alternatively manage a direct asynchronous transfer of data signals, for example, between resource 20 and module 14 in response to handshaking signals generated between module 14 and resource 20 in accordance with a suitable asynchronous transfer protocol.
Clock crossing circuitry 70 is typically implemented to manage clock frequency cross-overs at only one or few clock ratios P/Q, where P/Q corresponds to the ratio of the frequency of clock signal 32 to the frequency of clock signal 34. Such clock crossing circuitry 70, however, limits the frequencies at which clock signals 32 and 34 may be generated. The ability to dial in frequencies independently for each module 12 and 14 is desirable to allow integrated circuit chip 10 to cover different market segments and to facilitate different frequency bins for integrated circuit chip 10. Constraints on the frequencies at which clock signals 32 and 34 may be generated may also mean module 12 and/or module 14 may not be driven at relatively higher frequencies. Although clock crossing circuitry 70 may be implemented to manage many more clock ratios P/Q, such clock crossing circuitry 70 is typically more costly and more complex to implement on silicon and typically increases die size.
Clock crossing circuitry 70 also reduces performance of integrated circuit chip 10 due to the increase in the latency of transactions crossing multiple clock domains. Incorporating high skew and jitter parameters into clock crossing circuitry 70 further complicates its implementation. The logic complexity of the bus crossing clock crossing circuitry 70 also increases the pre-silicon and post-silicon logic design validation effort.
Furthermore, module 14 cannot access resource 20 if clock signal 32 ceases, for example, when module 12 enters an internal power down or sleep mode.